`ifndef RANDOMIZE
  `ifdef RANDOMIZE_MEM_INIT
    `define RANDOMIZE
  `endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
  `ifdef RANDOMIZE_REG_INIT
    `define RANDOMIZE
  `endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE

// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
  `define RANDOM $random
`endif // not def RANDOM

// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
  `define INIT_RANDOM
`endif // not def INIT_RANDOM

// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
  `define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY

// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
  `ifdef RANDOMIZE
    `ifdef VERILATOR
      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
    `else  // VERILATOR
      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
    `endif // VERILATOR
  `else  // RANDOMIZE
    `define INIT_RANDOM_PROLOG_
  `endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_

// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
  `ifndef ENABLE_INITIAL_REG_
    `define ENABLE_INITIAL_REG_
  `endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS

// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
  `ifndef ENABLE_INITIAL_MEM_
    `define ENABLE_INITIAL_MEM_
  `endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS

// Standard header to adapt well known macros for prints and assertions.

// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
  `ifdef PRINTF_COND
    `define PRINTF_COND_ (`PRINTF_COND)
  `else  // PRINTF_COND
    `define PRINTF_COND_ 1
  `endif // PRINTF_COND
`endif // not def PRINTF_COND_

// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing.
`ifndef ASSERT_VERBOSE_COND_
  `ifdef ASSERT_VERBOSE_COND
    `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND)
  `else  // ASSERT_VERBOSE_COND
    `define ASSERT_VERBOSE_COND_ 1
  `endif // ASSERT_VERBOSE_COND
`endif // not def ASSERT_VERBOSE_COND_

// Users can define 'STOP_COND' to add an extra gate to stop conditions.
`ifndef STOP_COND_
  `ifdef STOP_COND
    `define STOP_COND_ (`STOP_COND)
  `else  // STOP_COND
    `define STOP_COND_ 1
  `endif // STOP_COND
`endif // not def STOP_COND_

module SimTop();

  // 时钟和复位信号定义
  reg clock;
  reg reset; // 高有效复位

  // 时钟周期参数
  parameter CLK_PERIOD = 40; // 25MHz = 40ns周期

  // 时钟逻辑
  initial begin
    clock = 0;
    forever #(CLK_PERIOD/2) clock = ~clock;
  end

  // 复位逻辑
  initial begin
    reset = 1;            // 初始复位有效
    #(CLK_PERIOD*50000);      // 保持复位5个周期
    reset = 0;            // 释放复位
  end




  AXI_BUS #(
    .AXI_ADDR_WIDTH (31),
    .AXI_DATA_WIDTH (64),
    .AXI_ID_WIDTH   (2),
    .AXI_USER_WIDTH (1)
  ) peripheral();

  AXI_BUS #(
    .AXI_ADDR_WIDTH (48),
    .AXI_DATA_WIDTH (256),
    .AXI_ID_WIDTH   (14),
    .AXI_USER_WIDTH (1)
  ) memory();




  XSTop l_soc (
    .nmi_0_0                                     (1'h0),
    .nmi_0_1                                     (1'h0),

    .dma_awready                                 (/* unused */),
    .dma_awvalid                                 (1'h0),
    .dma_awid                                    (15'h0),
    .dma_awaddr                                  (48'h0),
    .dma_awlen                                   (8'h0),
    .dma_awsize                                  (3'h0),
    .dma_awburst                                 (2'h0),
    .dma_awlock                                  (1'h0),
    .dma_awcache                                 (4'h0),
    .dma_awprot                                  (3'h0),
    .dma_awqos                                   (4'h0),
    .dma_wready                                  (/* unused */),
    .dma_wvalid                                  (1'h0),
    .dma_wdata                                   (256'h0),
    .dma_wstrb                                   (32'h0),
    .dma_wlast                                   (1'h0),
    .dma_bready                                  (1'h0),
    .dma_bvalid                                  (/* unused */),
    .dma_bid                                     (/* unused */),
    .dma_bresp                                   (/* unused */),
    .dma_arready                                 (/* unused */),
    .dma_arvalid                                 (1'h0),
    .dma_arid                                    (15'h0),
    .dma_araddr                                  (48'h0),
    .dma_arlen                                   (8'h0),
    .dma_arsize                                  (3'h0),
    .dma_arburst                                 (2'h0),
    .dma_arlock                                  (1'h0),
    .dma_arcache                                 (4'h0),
    .dma_arprot                                  (3'h0),
    .dma_arqos                                   (4'h0),
    .dma_rready                                  (1'h0),
    .dma_rvalid                                  (/* unused */),
    .dma_rid                                     (/* unused */),
    .dma_rdata                                   (/* unused */),
    .dma_rresp                                   (/* unused */),
    .dma_rlast                                   (/* unused */),

    .peripheral_awready   (peripheral.awready ),
    .peripheral_awvalid   (peripheral.awvalid ),
    .peripheral_awid      (peripheral.awid    ),
    .peripheral_awaddr    (peripheral.awaddr  ),
    .peripheral_awlen     (peripheral.awlen   ),
    .peripheral_awsize    (peripheral.awsize  ),
    .peripheral_awburst   (peripheral.awburst ),
    .peripheral_awlock    (peripheral.awlock  ),
    .peripheral_awcache   (peripheral.awcache ),
    .peripheral_awprot    (peripheral.awprot  ),
    .peripheral_awqos     (peripheral.awqos   ),
    .peripheral_wready    (peripheral.wready  ),
    .peripheral_wvalid    (peripheral.wvalid  ),
    .peripheral_wdata     (peripheral.wdata   ),
    .peripheral_wstrb     (peripheral.wstrb   ),
    .peripheral_wlast     (peripheral.wlast   ),
    .peripheral_bready    (peripheral.bready  ),
    .peripheral_bvalid    (peripheral.bvalid  ),
    .peripheral_bid       (peripheral.bid     ),
    .peripheral_bresp     (peripheral.bresp   ),
    .peripheral_arready   (peripheral.arready ),
    .peripheral_arvalid   (peripheral.arvalid ),
    .peripheral_arid      (peripheral.arid    ),
    .peripheral_araddr    (peripheral.araddr  ),
    .peripheral_arlen     (peripheral.arlen   ),
    .peripheral_arsize    (peripheral.arsize  ),
    .peripheral_arburst   (peripheral.arburst ),
    .peripheral_arlock    (peripheral.arlock  ),
    .peripheral_arcache   (peripheral.arcache ),
    .peripheral_arprot    (peripheral.arprot  ),
    .peripheral_arqos     (peripheral.arqos   ),
    .peripheral_rready    (peripheral.rready  ),
    .peripheral_rvalid    (peripheral.rvalid  ),
    .peripheral_rid       (peripheral.rid     ),
    .peripheral_rdata     (peripheral.rdata   ),
    .peripheral_rresp     (peripheral.rresp   ),
    .peripheral_rlast     (peripheral.rlast   ),
    
    .memory_awready       (memory.awready     ),
    .memory_awvalid       (memory.awvalid     ),
    .memory_awid          (memory.awid        ),
    .memory_awaddr        (memory.awaddr      ),
    .memory_awlen         (memory.awlen       ),
    .memory_awsize        (memory.awsize      ),
    .memory_awburst       (memory.awburst     ),
    .memory_awlock        (memory.awlock      ),
    .memory_awcache       (memory.awcache     ),
    .memory_awprot        (memory.awprot      ),
    .memory_awqos         (memory.awqos       ),
    .memory_wready        (memory.wready      ),
    .memory_wvalid        (memory.wvalid      ),
    .memory_wdata         (memory.wdata       ),
    .memory_wstrb         (memory.wstrb       ),
    .memory_wlast         (memory.wlast       ),
    .memory_bready        (memory.bready      ),
    .memory_bvalid        (memory.bvalid      ),
    .memory_bid           (memory.bid         ),
    .memory_bresp         (memory.bresp       ),
    .memory_arready       (memory.arready     ),
    .memory_arvalid       (memory.arvalid     ),
    .memory_arid          (memory.arid        ),
    .memory_araddr        (memory.araddr      ),
    .memory_arlen         (memory.arlen       ),
    .memory_arsize        (memory.arsize      ),
    .memory_arburst       (memory.arburst     ),
    .memory_arlock        (memory.arlock      ),
    .memory_arcache       (memory.arcache     ),
    .memory_arprot        (memory.arprot      ),
    .memory_arqos         (memory.arqos       ),
    .memory_rready        (memory.rready      ),
    .memory_rvalid        (memory.rvalid      ),
    .memory_rid           (memory.rid         ),
    .memory_rdata         (memory.rdata       ),
    .memory_rresp         (memory.rresp       ),
    .memory_rlast         (memory.rlast       ),

    .io_clock                                    (clock),
    .io_reset                                    (reset),

    .io_sram_config                              (16'h0),

    .io_extIntrs                                 (64'b0),

    .io_pll0_lock                                (1'h1),
    .io_pll0_ctrl_0                              (/* unused */),
    .io_pll0_ctrl_1                              (/* unused */),
    .io_pll0_ctrl_2                              (/* unused */),
    .io_pll0_ctrl_3                              (/* unused */),
    .io_pll0_ctrl_4                              (/* unused */),
    .io_pll0_ctrl_5                              (/* unused */),

    .io_systemjtag_jtag_TCK                      (1'b0),
    .io_systemjtag_jtag_TMS                      (1'b0),
    .io_systemjtag_jtag_TDI                      (1'b0),
    .io_systemjtag_jtag_TDO_data                 (/* unused */),
    .io_systemjtag_jtag_TDO_driven               (/* unused */),
    .io_systemjtag_reset                         (reset),
    .io_systemjtag_mfr_id                        (11'h0),
    .io_systemjtag_part_number                   (16'h0),
    .io_systemjtag_version                       (4'h0),

    .io_debug_reset                              (reset),

    .io_rtc_clock                                (clock),

    .io_cacheable_check_req_0_valid              (1'h0),
    .io_cacheable_check_req_0_bits_addr          (48'h0),
    .io_cacheable_check_req_0_bits_size          (2'h0),
    .io_cacheable_check_req_0_bits_cmd           (3'h0),
    .io_cacheable_check_req_1_valid              (1'h0),
    .io_cacheable_check_req_1_bits_addr          (48'h0),
    .io_cacheable_check_req_1_bits_size          (2'h0),
    .io_cacheable_check_req_1_bits_cmd           (3'h0),
    .io_cacheable_check_resp_0_ld                (/* unused */),
    .io_cacheable_check_resp_0_st                (/* unused */),
    .io_cacheable_check_resp_0_instr             (/* unused */),
    .io_cacheable_check_resp_0_mmio              (/* unused */),
    .io_cacheable_check_resp_0_atomic            (/* unused */),
    .io_cacheable_check_resp_1_ld                (/* unused */),
    .io_cacheable_check_resp_1_st                (/* unused */),
    .io_cacheable_check_resp_1_instr             (/* unused */),
    .io_cacheable_check_resp_1_mmio              (/* unused */),
    .io_cacheable_check_resp_1_atomic            (/* unused */),

    .io_riscv_halt_0                             (/* unused */),

    .io_riscv_critical_error_0                   (/* unused */),

    .io_riscv_rst_vec_0                          (48'h80000000),

    .io_traceCoreInterface_0_fromEncoder_enable  (1'h0),
    .io_traceCoreInterface_0_fromEncoder_stall   (1'h0),
    .io_traceCoreInterface_0_toEncoder_cause     (/* unused */),
    .io_traceCoreInterface_0_toEncoder_tval      (/* unused */),
    .io_traceCoreInterface_0_toEncoder_priv      (/* unused */),
    .io_traceCoreInterface_0_toEncoder_iaddr     (/* unused */),
    .io_traceCoreInterface_0_toEncoder_itype     (/* unused */),
    .io_traceCoreInterface_0_toEncoder_iretire   (/* unused */),
    .io_traceCoreInterface_0_toEncoder_ilastsize (/* unused */)
  );



axi_ram #(
  .DATA_WIDTH      (64),
  .ADDR_WIDTH      (31),
  .STRB_WIDTH      (8),
  .ID_WIDTH        (2)
) u_axi_mmio (
  .clk             (clock),
  .rst             (reset),

  .s_axi_awid      (peripheral.awid   ),
  .s_axi_awaddr    (peripheral.awaddr ),
  .s_axi_awlen     (peripheral.awlen  ),
  .s_axi_awsize    (peripheral.awsize ),
  .s_axi_awburst   (peripheral.awburst),
  .s_axi_awlock    (peripheral.awlock ),
  .s_axi_awcache   (peripheral.awcache),
  .s_axi_awprot    (peripheral.awprot ),
  .s_axi_awvalid   (peripheral.awvalid),
  .s_axi_awready   (peripheral.awready),
  .s_axi_wdata     (peripheral.wdata  ),
  .s_axi_wstrb     (peripheral.wstrb  ),
  .s_axi_wlast     (peripheral.wlast  ),
  .s_axi_wvalid    (peripheral.wvalid ),
  .s_axi_wready    (peripheral.wready ),
  .s_axi_bid       (peripheral.bid    ),
  .s_axi_bresp     (peripheral.bresp  ),
  .s_axi_bvalid    (peripheral.bvalid ),
  .s_axi_bready    (peripheral.bready ),
  .s_axi_arid      (peripheral.arid   ),
  .s_axi_araddr    (peripheral.araddr ),
  .s_axi_arlen     (peripheral.arlen  ),
  .s_axi_arsize    (peripheral.arsize ),
  .s_axi_arburst   (peripheral.arburst),
  .s_axi_arlock    (peripheral.arlock ),
  .s_axi_arcache   (peripheral.arcache),
  .s_axi_arprot    (peripheral.arprot ),
  .s_axi_arvalid   (peripheral.arvalid),
  .s_axi_arready   (peripheral.arready),
  .s_axi_rid       (peripheral.rid    ),
  .s_axi_rdata     (peripheral.rdata  ),
  .s_axi_rresp     (peripheral.rresp  ),
  .s_axi_rlast     (peripheral.rlast  ),
  .s_axi_rvalid    (peripheral.rvalid ),
  .s_axi_rready    (peripheral.rready )
);



axi_ram #(
  .DATA_WIDTH      (256),
  .ADDR_WIDTH      (48),
  .STRB_WIDTH      (32),
  .ID_WIDTH        (14)
) u_axi_ram (
  .clk             (clock),
  .rst             (reset),

  .s_axi_awid      (memory.awid   ),
  .s_axi_awaddr    (memory.awaddr ),
  .s_axi_awlen     (memory.awlen  ),
  .s_axi_awsize    (memory.awsize ),
  .s_axi_awburst   (memory.awburst),
  .s_axi_awlock    (memory.awlock ),
  .s_axi_awcache   (memory.awcache),
  .s_axi_awprot    (memory.awprot ),
  .s_axi_awvalid   (memory.awvalid),
  .s_axi_awready   (memory.awready),
  .s_axi_wdata     (memory.wdata  ),
  .s_axi_wstrb     (memory.wstrb  ),
  .s_axi_wlast     (memory.wlast  ),
  .s_axi_wvalid    (memory.wvalid ),
  .s_axi_wready    (memory.wready ),
  .s_axi_bid       (memory.bid    ),
  .s_axi_bresp     (memory.bresp  ),
  .s_axi_bvalid    (memory.bvalid ),
  .s_axi_bready    (memory.bready ),
  .s_axi_arid      (memory.arid   ),
  .s_axi_araddr    (memory.araddr ),
  .s_axi_arlen     (memory.arlen  ),
  .s_axi_arsize    (memory.arsize ),
  .s_axi_arburst   (memory.arburst),
  .s_axi_arlock    (memory.arlock ),
  .s_axi_arcache   (memory.arcache),
  .s_axi_arprot    (memory.arprot ),
  .s_axi_arvalid   (memory.arvalid),
  .s_axi_arready   (memory.arready),
  .s_axi_rid       (memory.rid    ),
  .s_axi_rdata     (memory.rdata  ),
  .s_axi_rresp     (memory.rresp  ),
  .s_axi_rlast     (memory.rlast  ),
  .s_axi_rvalid    (memory.rvalid ),
  .s_axi_rready    (memory.rready )
);




















/*
uart_dpi
  #( .tcp_port(5678),
     .port_name("UART DPI number"),
     .welcome_message( "--- Welcome to my UART DPI port ---\n\r" )
   )
uart_dpi_instance2
(
        // WISHBONE common
        .wb_clk_i       ( wb_clk ), 
        .wb_rst_i       ( wb_rst ),

        // WISHBONE slave
        .wb_adr_i       ( wb_us2_adr_i[4:0] ),
        .wb_dat_i       ( wb_us2_dat_i ),
        .wb_dat_o       ( wb_us2_dat_o ),
        .wb_we_i        ( wb_us2_we_i  ),
        .wb_stb_i       ( wb_us2_stb_i ),
        .wb_cyc_i       ( wb_us2_cyc_i ),
        .wb_ack_o       ( wb_us2_ack_o ),
        .wb_err_o       ( wb_us2_err_o ),
        .wb_sel_i       ( wb_us2_sel_i ),

        // Interrupt request
        .int_o          ( pic_ints[`APP_INT_UART2] )
 );
*/



endmodule
